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In state-of-the-art CIS with 4T pixels, values of the lag as low as 0. Thus, the lag can be neglected compared to the read noise in the low light context. The transient noise related to the lag is believed to behave as a shot noise [ 11 ], similarly to buried channel CCDs [ 13 ].
It is also believed that trapping mechanisms in the silicon oxide interface under the transfer gate also contribute to the transfer non-idealities [ 10 , 14 , 15 , 16 ], giving rise to a Random Telegraph Signal RTS -like noise. Finally, the readout of the SN reset and transfer voltages is affected by random fluctuations due to the readout chain noise; starting with the in-pixel SF and noise coupling of the TX and RST lines with the SN, the power supply noise and ending with the column-level circuitry and analog-to-digital converters ADCs.
The column-level amplification is introduced in order to minimize the contribution of the next circuit blocks to the input-referred total noise, e.
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The column-level amplifier also limits the bandwidth in order to minimize the thermal noise [ 8 ]. A switched capacitor amplifier is usually used. When the AZ switch is opened, the noise is sampled at the integration capacitor and transferred to the output. This sampled noise is also canceled thanks to the CDS. Low noise CIS readout chains may also include correlated multiple sampling CMS that can be implemented with analog circuitry [ 17 , 18 ] or performed after the ADC [ 19 ].
CMS consists of averaging M samples after the reset and M other samples after the transfer with a sampling period T S , then calculating the difference between the two averages. With a careful design, the readout noise originating from the pixel and column-level amplifier is the dominant noise source in CIS. Figure 3 shows the calculated probability of a true photo-electron count and a single photo-electron detection as a function of the input-referred readout chain noise by assuming a Gaussian distribution of noise and using the error function.
Recently reported works are today closer than ever to these limits [ 7 , 8 , 20 ]. A detailed noise analysis of the readout noise is therefore necessary in order to determine the key design and process parameters that can be used for further noise reduction. Probability of a true photo-electron count and single photo-electron detection as a function of the input-referred readout noise.
For each noise source, the variance at the output of the readout chain is first calculated and then referred to the input as a noise charge. Hence, the pixel conversion gain is a key parameter in the noise analysis. The pixel conversion gain can be calculated using a small-signal analysis of the pixel. It is crucial to take into account the effect of parasitic capacitances.
Figure 4 presents a schematic of a 4T pixel section view showing all of the parasitic capacitances connected to the sense node. These include the overlap capacitances of the transfer and reset gates, C T o v and C R o v , respectively, the sense node junction capacitance, C J , and the parasitic capacitance related to the metal wires, C W.
These capacitances are independent of the in-pixel SF. Their sum is defined as:. Cross-section of a conventional 4T pixel showing the different parasitic elements contributing to the sense node capacitance. Figure 5 presents a simplified small-signal schematic of the CIS readout chain of Figure 1. This small-signal schematic is used to calculate the conversion gain together with the noise and signal transfer functions.
Based on the detailed analytical calculation presented in [ 8 ], the conversion gain of a conventional CIS 4T pixel can be expressed as:. Small-signal analysis of the CIS readout chain depicted in Figure 1 showing the different readout noise sources considered in the analysis. C e is the extrinsic capacitance per unit width of the in-pixel source follower transistor. It includes the overlap and fringing capacitances as depicted in Figure 4.
C o x is the SF oxide capacitance per unit area. This empirical model is easy to use for hand calculation and remains valid even for advanced CMOS technologies for adequate gate widths and lengths [ 22 ]. The parameter K F can be expressed as [ 21 , 23 ]:. It has been shown in [ 21 ] that K G is close to unity when the transistor is operating in the weak and moderate inversion regime. It is important to establish a relationship between the parameters used by the simulator and the simple equation used for hand calculations in order to best exploit the noise calculation results.
The oxide trap density is the key process-dependent parameter. In low noise CIS readout chains, the transistors located outside the pixels array can be designed with gate dimensions much larger than the in-pixel source follower transistor. Based on the detailed analytical calculation [ 26 ], it can be expressed as:.
T S is the sampling period of the correlated sampling.
T S in Figure 6. The thermal noise of a MOS transistor operating in saturation is modeled by a drain current source that adds to the signal. The drain current noise PSD is commonly expressed as [ 21 ]:. In a conventional CIS readout chain, besides the power supply and bias voltage noise, there are two dominant thermal noise sources: the in-pixel SF transistor operating in saturation and the column-level amplifier. The two dominant noise sources are uncorrelated; thus, their noise PSDs add.
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We assume that the bandwidth of the in-pixel SF stage is limited by the column-level amplifier. We consider that the column-level gain is provided by a closed-loop operational transconductance amplifier OTA. Using the small-signal analysis of the SF stage and the column-level amplifier [ 8 ], the thermal noise voltage variance at the output of the column-level amplifier is calculated.
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It is then referred to the input using the column-level and conversion gain Equation 2 , resulting in:. Here, C L and C i n are the integration and load capacitances of the column-level amplifier. During the readout, the charge transferred to the SN may be corrupted by all of the leakage currents through the junctions and gate oxide due to tunneling. Since these leakage currents are due to barrier control processes, they give rise to shot noise.
As shown in the small-signal schematic of Figure 5 , the leakage current shot noise can be modeled by two noise current sources: I n , G D and I n , G S. I n , G D represents the shot noise of all of the leakage currents flowing between the SN and the ground, which includes the SN junction leakage and the SF gate oxide tunneling current that sinks into the bulk and the drain.
I n , G S represents the shot noise associated with part of the SF gate oxide tunneling current that flows to the source.
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The unilateral PSD of the current shot noise can be expressed as [ 27 ]:. It can be shown that both shot noise components I n , G D and I n , G S have the same transfer function magnitude, between the noise current source and the output of the column level amplifier. The leakage current shot noise PSD at the output of the column level amplifier can therefore be simplified as:. Note that I L is the sum of all of the sense node leakage currents. Note that the shot noise current sources feature a white PSD.
However, when integrated in the SN capacitance, they give rise to a Wiener process [ 28 ]. The variance of this noise is thus expected to rise with the readout time.
How to reduce noise in an electrical circuit
For thermal noise, the column-level gain A c o l , the capacitance C and the CMS order M all have the same impact on the input-referred noise. In order to validate this result, transient noise simulations [ 29 ] have been performed on a conventional CIS readout chain with a 4T pixel using a standard thick oxide NMOS source follower transistor, a column-level amplifier based on an OTA with a feedback capacitance C f and the passive CMS circuit presented in [ 17 ]. Figure 8 a shows the impact of the column-level gain and bandwidth control on the input-referred noise when a simple correlated double sampling is used after the column-level amplifier.
Figure 8 b shows the impact of the correlated multiple sampling on the input-referred thermal noise for different column-level gains. These simulation results show that the thermal noise can be reduced drastically using only the column-level parameters. As shown in Section 3. The thermal noise can be reduced to extremely low levels by implementing column-level circuit techniques as shown in Figure 8 a,b. This point remains an active research topic.